1. Field
Aspects of the present invention generally relate to integrated circuits and, more particularly, to the testing of integrated circuit interfaces.
2. Background
The semiconductor industry continually improves the scaling of device feature sizes in successive generations of integrated circuits. Improved scaling results in smaller devices and higher device densities, which produce a higher incidence of circuits composed of these devices to be compromised by faults. Accordingly, there is an increased emphasis on diagnosing circuit faults during manufacture to fully realize the benefits of scaling improvements. To help address the increased demand for determining faults, enhancements have been made to circuit diagnostic capabilities, such as automatic test pattern generation (ATPG), test path sensitization, and controllability of the device being tested. Typically, these testing capabilities include storage devices arranged in scan chains having accompanying control logic and clocking schemes. Scan-based testing provides stimulus and retrieves resulting indications of die functionality based on a fault model at the device-level, gate-level, or interconnect layer. Depending on the fault model implemented; faults, such as opens, shorts, fabrication defects, and stuck-at faults may be controllable and observable by scan-chain-based diagnosis.
Diagnostic improvements have generally been applied to core logic while input/output (I/O) blocks have lagged behind in the application of diagnostic developments. I/O blocks have particular situations and constraints that increase challenges to diagnosis. For instance, requirements on circuits in I/O blocks to produce consistent performance levels across generations of scaled semiconductor fabrication can mean the amount of die area dedicated to performance can correspondingly reduce the area available to implement diagnostic circuits.